#: 5268 S15/Hot Topics
    16-Jul-90  20:44:07
Sb: ##5233-32 bit bus
Fm: Kevin Pease 70516,1633
To:  70310,317



        Frank I have been reading the mail on the sidelines for a long time and
not comenting. First the 32 bit bus is something that over the next few years
will become necessary to suport new hardware and graphics standards. The way
this works is the MM/1 uses a 16 bit bus. So the MM/1 is using only half of the
32 bit bus. Eventually 68030's and 68040's will become more popular and the
need for a 32 bit bus will become aparent. Since we have a 32 bit bus defined
as part of the MM/1 specification the people that have bought boards for the
MM/1 will not be stuck with un-usable hardware. It wil plug in and be useable
by the new 32 bit processors. So the 32bit bus definition is so that people
don't have to throw away the boards that they may buy. I have never read the
ads by Paul but they probably should read that the MM/1 bus has been define for
full 32 bit operation. Also the 68040 does not suport dynamic bus sizeing. What
this means is that unless one uses a verry large amount of hardware external to
the processor to simulate the 68030/68020 automatic bus sizeing one can only
access a 16 bit wide device as a word aligned word access or properly aligned
byte access. One can not access the device as a 32 bit device and have the
processor make the two accesses that would be required to assemble the long
word. what this means is that if one has a 16 bit graphics board one could only
use word accesses to move memory around. with instruction execution overhead
the move would be slower than if the device was 32 bits wide. It would take 2
times as long to do the same size move.
        I don't know how you made the calculatins but they are verry
misleading. if one is moveing more than a few bytes of data around the 32 bit
bus will be two times as fast as the 16 bit bus for the same bus access speed.
Example: bus speed is 100 ns. on a 16 bit bus to move 1000 bytes it would take
500 accesses or 50000 ns. The same 1000 bytes would require 250 accesses or
25000 ns. the instruction over head for the two moves would be identical
assuming that the processor had an instruction cache. This explanation is a
little over

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