On 04/09/2020 13:36, Tauno Voipio wrote:
> On 4.9.20 12.10, druck wrote:
> In the 32 bit ARM (ARM7TDMI and relatives), the conditionality is in the
> top 4 bits of most instructions.

Most of the NV (never) variants have been repurposed as new instructions
now, as they were never that useful.

> In the same chips, the pipelining peeks in two places:
>   - offsets of PC-relative addresses,
>   - return addresses of exceptions.


Well remembered. It was a side effect of the very simple logic in ARM2 
which had a 3 stage pipeline so value of the PC register was always +8* 
of the currently executing instruction (ignoring Thumb which is +4).

Its a shame there wasn't the budget for a few extra transistors to 'fix'
this at the time, because this behaviour has had to be preserved on 
every subsequent ARM, no matter how many stages it has.

* There is one place where it is +12, can't remember where though!

---druck

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