Theo  wrote:
> So no change across the Pi families, possibly excepting the Pi 1.  As far as
> the CPU core is concerned you can make 32, 64 or 128 bit accesses from cache
> in a single cycle.  The bottom of the L2 can make 128 bit wide requests from
> DDR memory, which will cause a burst of four 32 bit requests back-to-back.
> The Pi 4 has LPDDR4-3200, which means those 4 requests will take:
>
> 4*(1/(3200*10^6)) = 1.25ns
>
> Generally the setup time for a DRAM is the expensive part, so once you have
> the request in the extra cycles for fetching multiple words don't cost much
> more.
>
> (I can't seem to find the data sheet for the Pi 4's DRAM part to see what
> the initial latency is)

Some interesting details in this thread, look for posts by dom especially:
https://www.raspberrypi.org/forums/viewtopic.php?f=63&t=271121

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