Charlie wrote:
>  wrote in message 
> news:ad98bdc8-a8ab-4434-b831-64a992cc4633{at}a37g2000pre.googlegroups.com...
> On Nov 14, 6:11 pm, "Michael J. Mahon"  wrote:
> 
>>Toinet wrote:
>>
>>>Dear All,
>>
>>>I own a Microneye camera but I lack its software. I would like to know
>>>whether some of you could provide me with a link to download it.
>>
>>>A search among the archive of csa2 brought me to several threads and
>>>links but all return in error.
>>
>>>I thank you in advance for your help.
>>
>>Wasn't that the de-capped DRAM chip adapted for use as a camera
>>(from back when CCDs were very expensive)?
>>
>>Circuit Cellar (Byte Magazine) ran an article on it, IIRC, but
>>the principle should be:
>>
>>1. Write all 1's (or all 0's) to the DRAM,
>>2. Wait for the desired exposure time,
>>3. Read back the DRAM--any differences are proportional
>>to the received illumination.
>>
>>The relationship between address and the image geometry
>>will need to be determined empirically.
>>
>>-michael
>>
>>******** Note new website URL ********
>>
>>NadaNet and AppleCrate II for Apple II parallel computing!
>>Home page: http://home.comcast.net/~mjmahon/
>>
>>"The wastebasket is our most important design
>>tool--and it's seriously underused."
> 
> 
> | Yep, it's a de-capped RAM chip. Wouldn't there be a threshold per bit
> | - no "proportional"? Or maybe you could scan at different exposure
> | times to assemble a gray scale image.

This would be the natural way to proceed with a 1-bit threshold, but
it would take 2^n-1 exposures to get n bits, so anything beyond crude
grayscale would take a while.

On the other hand, making multiple exposures and examining the
average number of 0's and 1's would allow for pretty good "automatic
exposure" adjustment by the software.

> | Does anyone know if capped non-Micron RAM chips also be used this way?
> | (I've got a box of "iffy" capped RAM chips)
> 
> If I recall correctly, in the Circuit Cellar article a Micron RAM chip was 
> used because it was the only one that Steve found that had the memory cells 
> laid out in a regular order 2 sets of 256 x 128 (Steve only used one). 
> Other chips at the time had the cells in different orders such that the 
> position in the chip didn't correspond with the memory address.  That would 
> have required a more complex program to put the pixels in the correct order.

True, and I can see how a "wirehead" like Steve Ciarcia would have
though that was a big deal.  But Apple II programmers know that *any*
permutation of bits in pixel addressing is a small matter of software
or tables.  ;-)  It would be almost as easy to use *any* DRAM in this
way.

-michael

NadaNet and parallel computing for Apple II computers!
Home page: http://members.aol.com/mjmahon

"The wastebasket is our most important design
tool--and it's seriously underused."
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