Folderol  wrote:
> On Fri, 28 Feb 2020 22:01:34 GMT
> Alister  wrote:
>>On Fri, 28 Feb 2020 12:27:48 -0500, Dennis Lee Bieber wrote:
>>> On Fri, 28 Feb 2020 11:39:05 GMT, Jan Panteltje
>>>  declaimed the following:
>>>>The GPIO as _digital_ input sees a 'logic zero' below some voltage and a
>>>>'logic one' above  some voltage.
>>>>Th exact voltage can vary,  also  depends on temperature and production
>>>>spread, but is somewhere between 0 and 3.3 V
>>>>
>>> Presuming common CMOS thresholds of 30 and 70%: <0.99V is LOW, 2.31V
>>> is HIGH. What the circuit does between those thresholds is indeterminate
>>> (I'd hope it holds the last valid state until the far threshold is
>>> crossed).
>>
>>that is exactly what does NOT happen.
>>the logic sate will flip at some in-determinant point between the two
>>thresholds. The thresholds are simply points at which the state is
>>guaranteed.
>
> This is mostly true, but not when the device specifies a schmitt trigger
input,
> when indeed the output is held until the second threshold is reached.

Yes, though the Pi doesn't have any schmitt trigger inputs on its
GPIOs.

The closest that you get to specs for these this with the chips
used in the Pis are the datasheets for the Compute modules that
use the same SoC. Even then I wouldn't trust those specs blindly.

CMOS inputs also aren't meant to linger in the "intermediate zone"
between LOW (under 1/3 supply voltage = 1.1V @ 3.3V supply)  and
HIGH (over 2/3 supply voltage = 2.2V). If they do then there is
potential for any variety of undesireable and unpredictable
behaviours. What you need in this case is an external Op-Amp chip
configured as a comparator, which will do the level detection of
the analogue signal and produce an output which can be compatible
with the Pi's GPIO (if you make sure that the LOW and HIGH voltages
fall within the ranges above, and that the signal can never go
higher than the Pi's 3.3V supply).

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