alex.freed.007{at}gmail.com wrote:
> On Jan 10, 2:47 am, "Michael J. Mahon"  wrote:
>> If the Apple could dynamically reconfigure the FPGA card, it would
>> make it truly a different substance.
> 
> It just might be possible to add wings to this particular pig...

;-)

>> The practical issues of configuration file size and programming speed
>> are, of course, of real importance.  I was about to ask what a typical
>> file size is...
> 
> Always fixed size for a particular chip. For the 500E on my prototype
> the configuration file is 278K.

That's quite reasonable, actually.

>>  And how many bits must be banged per "bit" of config?
> 
> After some initial setup, JTAG is like SPI. 2 bytes to send for each
> bit -
> clock up and clock down with the data bit set or reset.

Right--standard bit-banging.

>> And are there real-time constraints--for example, can the programming
>> be "paused" and resumed after a disk I/O?
> 
> You can send one clock an hour - no limitation AFAIK.

That's good, but it looks like 278KB could be bit-banged in a little
less than 40 seconds, including the hard-disk I/O!  That's a pretty
reasonable time for reconfiguration.  ;-)

My loop uses about 17 cycles per bit, with no unrolling.  8x unrolling
would take the time down a little.  Arranging to "generate" the JTAG
clocking on each write to /DEVSEL space and sampling the data from one
of the data bits would drop the time/bit to just 6 cycles per bit, for
less than 15 second configuration times!

-michael

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