Dennis Lee Bieber  wrote:
>  The processor core is just one part of the SoC. How large is the L2
> cache? This document only mentions it could be 512kB, 1, 2, or 4MB -- and
> I'm sure that is a design decision when laying out the SoC, not some
> runtime boot parameter. Does the R-Pi4 have the ACP -- which is considered
> an optional interface. Where are the SPI/I2C/UART systems documented?
>
>  Heck -- you need an account just to obtain the ARM v8 architecture
> documentation...
>
>  Where is the equivalent to http://www.ti.com/lit/pdf/spruh73 (which
> covers the Beaglebone Black chip set)?

Ask not here but in
https://www.raspberrypi.org/forums/viewforum.php?f=29
https://www.raspberrypi.org/forums/viewforum.php?f=72

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