On Feb 27, 1:59=A0am, demp...{at}actrix.gen.nz (David Empson) wrote:

> I'd have to do more tests and don't have time in the next few days.

Here's a simple one I did:

10 PRINT PEEK (49206)
20 X =3D X + 1 : IF X > 100 THEN PRINT "-----" : X =3D 0
30 GOTO 10

When run, it should display "132" for fast mode and "4" for slow
(content of $C036). Periodically it will print dashes, which help
visually estimate running speed too.

Now the fun part - while running it, I tried changing speed through
Control Panel. Randomly the change may take or not take effect. So, it
turns out that WYSINWYG. :-)
The only way I found to be sure about changed speed is by stopping the
scroll with CTRL+S and then accessing the Control Panel setting.

Which all leads me to think something in input/output routines is
massively overwriting the speed register and it doesn't do it
gracefully, clashing with other speed change candidates (including
Control Panel).

> > Any faintest idea why speeding while waiting for keypress? It's beyond
> > me, totally.
>
> The only reasons I can think of would relate to the speed of the
> blinking cursor and the responsiveness to editing keypresses, e.g. with
> fast keyboard auto-repeat settings. They probably wanted to be in a
> fixed mode so the timing would be consistent, and it makes more sense to
> force fast mode so that everything will go a little quicker.

Speed doesn't change cursor blinking speed, same in Applesoft and
Monitor.

> > Umm, I think the Mega II signals to FPI (and then reaches CPU possibly
> > by means of RDY) that there is a DMA and FPI allows or disallows
> > depending on the bank register.
> > But I'm shooting in the dark.
>
> I'd need to dig out my IIgs hardware reference and have a closer look at
> the schematics.

Can you send me (good print quality) scanned 03 schematics someday?

> Certainly for a normal CPU access, the FPI is in charge.

For the internal fast bus and memory expansion connector, yes. But
it's the Mega II which is connected physically to the seven slots.

> DMA is more complicated due to being initiated by an I/O card in a
> certain phase of the 1 MHz cycle, while the FPI and CPU might be off
> doing something else out of sync at 2.8 MHz.
>
> It may be necessary to abort a fast CPU cycle in order to get out of the
> way of the DMA access.

Or they could be just playing with Phi2 length and smart signaling
between FPI and Mega II. Tech notes had some interesting info about
this.
When some excess spare time appears I could investigate with a logic
analyzer.
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