> The problem I am having is:  What happens if I get
 > interrupted in a place where I am adjusting the size of
 > the fifo?  I am unable to disable interrupts at this time
 > as I cannot afford to miss a single interrupt.

This depends on the machine/hardware.

"Missing" an interrupt is normally a problem with multi-level
edge-triggered interrupt systems. With level-triggered interrupt priority
ordering, you won't miss a thing. Most interrupt driven systems will
normally provide an interrupt queue which, if an interrupt is triggered
while interrupts are disabled, will cause the interrupt to be triggered
immediately (or so many clocks after) the interrupt line on the bus goes
high again. This works even for stupidly designed busses like the PC ISA
bus which operates (correctly) in edge-triggered mode only. The real risk
of interrupt loss is when the interrupt handler EOI's the interrupt
controller without having handled (all of) the interrupt(s), and to a
lesser extent if the interrupt is not handled quickly enough and is
'overwritten' by a subsequent interrupt before the device can be
interrogated. The latter depends on the hardware you're talking to, but is
common with older ethernet hardware and some junk/buggy UARTs, like the
8250, and even then it depends on the types of interrupts involved.

So I doubt you'll have a problem with disabling interrupts for short
periods. Depending on the actual microprocessor, it may be the *only* way
you can ensure that updating the pointers/indices that are used by the
interrupt handler is an atomic operation. This is the point where you need
to spend the most time optimising your code (avoid jumps, loops or anything
else that will loose whatever intruction caching the CPU does).

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