From: "Rich Gauszka" 

Hopefully they'll use an exceptional algorithm to access the NAND

http://www.linuxdevices.com/articles/AT2185129745.html
Okay. So NAND is not perfect. Actually, as a raw material, NAND flash comes
out of the fab with a lot of problems that can only be corrected with
up-to-date flash management software. Below is a sampling of these
problems.

    * Physical vs. logical mapping -- Flash media is organized in physical
blocks, or erase units, which are further divided into physical sectors.
Standard file system calls specifying hard disk sector numbers and
cylinders cannot be used to access data on the flash media. Dynamic virtual
mapping is required, in order to map the file system model to the flash
physical model.

    * Time-consuming and life-reducing P/E cycle -- To write, or program new
data, existing data must first be erased. The process of erasing and
programming is known as the P/E cycle. Each flash sector can withstand a
limited number of P/E cycles before it becomes unusable. When this happens,
overall capacity is gradually reduced, existing data becomes prone to
random errors and application and OS code can quickly become corrupted,
increasing the likelihood of total application failure. As manufacturing
geometries shrink and the density of flash media increases, more complex
error checking and re-writing is required. This further reduces the usable
lifespan of the media, degrades performance and increases power
consumption. Advanced dynamic and static wear leveling is required to
extend the lifespan of the media, especially when it stores critical data
such as OS and configuration files.

    * Randomly scattered bad blocks -- MLC NAND media are knowingly shipped
from the fab, with up to 5 percent randomly scattered bad blocks. In
addition to the "initial" bad blocks, normal wear from writing
and erasing cause additional blocks to become corrupted, and eventually
unusable. Bad blocks need to be located and tracked, so that they are
avoided during write operations.

    * Bit flipping and bit pairing -- A bit can reverse its charge or be
reported as reversed. If even a single bit reverses in a block that stores
boot code, OS, or configuration files, the reliability of the device could
be compromised. In MLC NAND, two or more bits are stored in each physical
cell of the flash media. If a single bit is corrupted (by a power
disturbance or software error during a write operation) it corrupts its
paired bit in the cell, even if the paired bit had already been written
successfully. What's worse, bit-pairing schemes differ between NAND flash
vendors, and even between different NAND generations from the same vendor.
Innovative error detection code (EDC) and error correction code (ECC) must
be used to ensure data reliability without negatively impacting
performance. EDC and ECC need to take into account the different types of
NAND flash errors (bit flipping, bit pairing, charge drift, etc.) and the
different ways that they manifest from vendor to vendor.

    * Data retention errors -- Over time, current leakage or charge drift
can slowly change a cell's voltage level, which could incorrectly be
interpreted as a different logical value. This impacts data retention,
which is a measure of how long data can be stored without deteriorating to
the point where error detection and correction can no longer correct the
errors.

    * Power failure immunity -- In flash memory, the P/E cycle uses "erase
before write" algorithms, which can lead to longer write cycles more
likely to be interrupted during power failures, leading to lost or
corrupted data and code. Advanced flash management technologies implement
"erase after write" algorithms to ensure data integrity during
normal operation and in the event of a power failure.

LC NAND flash technology -- more trouble

Increasing NAND flash bits per cell density reduces cost and size, but
exacerbates flash limitations, degrading reliability, performance and flash
lifespan -- further complicating ease-of-integration. In flash devices that
implement standard Single Level Cell (SLC) technology, one bit of data is
stored per cell, using two voltage levels. Multi-Level Cell (MLC) stores
two bits of data per cell, using four voltage levels. MLC is the most
advanced, cost-effective NAND technology to date. But, it also presents
unsurpassed complexity, requiring far more complex management technologies.
"mike"  wrote in message
news:avf8v2lmf8l3icgctcv54r52c7gmr2gbbs{at}4ax.com...
>
> NOR flash - 100,000 cycles
> NAND flash - 1.000.000 cycles
>
>
> http://www.eepn.com/Locator/Products/Index.cfm?Ad=1&ArticleID=34509
>
> ===
> ...
> Made up of gates, there are basically two types of flash memory devices:
> NOR and NAND. In operation, NOR flash performs like the typical RAM
> found in a computer, allowing direct access to a byte or bytes of space
> regardless of their position in the storage space. In use, NOR flash may
> be used to store a component's application-specific software, such as
> firmware in a router or a computer's BIOS. NOR flash specifies a working
> life of around 100,000 write cycles before developing bad blocks.
>
> About a year after Intel unveiled the first NOR flash device, Toshiba
> developed NAND flash, which relies on flash-translation software that
> makes the device appear as a hard-disk drive to the operating system.
> This type of flash exhibits three distinct advantages over its NOR
> counterpart: a longer lifespan in the realm of one million read/write
> cycles, faster read/write times, and lower cost. In addition, NAND flash
> is capable of retaining larger chunks of data for either long- or
> short-term storage. The NAND devices are more useful for storing data
> collected by or downloaded to a product, i.e., information from a data
> logger, photos/video from a digital camera, music files on a MP3 player,
> and so forth.
>
> A more recent and third type of flash is OneNAND flash. Created by
> Samsung, it supports faster data throughputs and higher densities, two
> major requirements for high-resolution photography, video, and other
> media applications. OneNAND could be viewed as a kind of hybrid of both
> NOR and NAND technologies. Essentially, a single OneNAND chip integrates
> a NOR flash interface, NAND-flash controller logic, a NAND-flash array,
> and as much as 5 KB of buffer RAM. In terms of speed, it can deliver
> sustained read rates up to 108 MB/s.
> ...
> ===
>
>  /m
>
>
>
> On Sun, 11 Mar 2007 11:21:35 -0400, "Rich Gauszka"
>  wrote:
>
>>What's the current guaranteed erase - rewrite cycle limit on flash?  I
>>thought I saw something like 10,000 times before all bets are off.  If so,
>>a
>>rather unsophisticated program could blow away your flash drive in minutes
>>
>>
>>"mike"  wrote in message
>>news:ht68v218901gqiv2340hu4u2p5b59h60gv{at}4ax.com...
>>>
>>>
http://www.informationweek.com/news/showArticle.jhtml?articleID=197801483
>>>

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