Tom Miller wrote in a message to Mike Bilow:
 > You can probably reduce the CPU load by switching down the IDE I/O 
 > mode if your CMOS setup allows it.  For example, enabling multiple 
 > sector I/O is a big help, and dropping to PIO Mode 1 or 0 may also 
 > help.  Although PIO Mode 3 will transfer the data faster, the 
 > overall system speed may improve with a more restrictive PIO Mode.  
 > If you have DMA support on IDE, then it will usually be an advantage 
 > to enable it.
 TM> Ok, then I wasn't wrong... someplace I got the idea that PIO 
 TM> required the cpu to handle each byte, rather than triggering a 
 TM> DMA transfer...  So even though the PIO Mode 3 is faster, it 
 TM> requires cpu intervention for each byte processed... unlike a 
 TM> DMA type HD to ram transfer (which is what I am used to). 
Yes.  While PIO ties up the CPU for moving the data byte-by-byte, ISA DMA 
will tie up the system bus and prevent the CPU from doing useful work.  
Usually, ISA DMA works through the motherboard controller chips, which will 
tend to be slower than PIO.  ISA DMA is intended for fairly low speed devices 
such as the floppy controller and sound cards, and hard drives were something 
of an afterthought.
 TM> So I guess maybe I have the best of "both" ide worlds... I
 TM> have an GSI 21 (E)IDE controller that runs on an ISA bus,
 TM> activates multiple block i/o, and the docs claim its builtin
 TM> bios will allow me to access single ms-dos partitions upto 8
 TM> gigabytes... :)   Ignoring the fact that an ISA based server
 TM> probably would not be able to handle a very big load :)
If you get out of the ISA world, PCI EIDE controllers can do bus-mastering 
DMA.  This uses the full speed of the bus, bypassing the motherboard DMA 
controller hardware.  The downside is that, in order to clear the way for a 
bus-mastering DMA transfer, the CPU and its associated logic have to be 
completely taken off the bus.
In a properly configured PCI system, the CPU will usually be processing out 
of its local L1 or L2 cache, and will not be held up waiting for the bus very 
often.  The likelihood of a CPU cache miss is minimized by using large CPU 
caches, which is why the Pentium Pro is commonly regarded as a server chip, 
and by limiting the contiguous blocksize of DMA transfers, which is why SCSI 
controllers do scatter-gather.  Assuming that the CPU cache is in write-back 
mode, you can get significant speed from splitting the bus bandwidth like 
this, but complexity is introduced in order to ensure cache integrity.  By 
using what are termed "snooping" and "snarfing" techniques, the cache logic 
monitors the DMA transfer to see if any of the data in the cache are being 
accessed by the transfer, and then immediately invalidating that cache line.
 
-- Mike
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