On 11/07/18 22:51, Michael J. Mahon wrote:
> Virtually all modern processors have multi-level caches.

OK.

>
> A reference to an address not yet in cache will result in a cache fault at
> all levels, causing a main memory access that transfers a cache line of
> data to the primary (largest, slowest) cache, and the next level cache to
> receive its (typically smaller) line of data containing the referenced
> word(s).  This continues until the smallest, fastest level 0 cache is
> loaded with the referenced word, which is usually bypassed directly to the
> processor’s register file (which can be thought of as the ultimate cache,
> managed by the compiler).
>
> Every doubling of data size effectively halves the size of all caches and
> data memory, so the performance cost is considerable for any program that
> stresses any level of cache.
>

OK. That is really another way of saying Richard Kettlewells point, that
the bottleneck is memory access, and that sparse data in memory makes
for more memory accesses.


> And don’t expect Moore’s “Law” to save you. We are past the point of
> increasing clock frequency—now all the density improvements just deliver
> more cores on a chip, so unless you love parallel algorithms, you’re out of
> luck. ;-(


Well I knew that already. More to the point it looks like increasing
memory speed is also at an end.

And although HD=>SSD was a huge step up, thats pretty much done and dusted.

Only one place left to go. Tackle bloatware :-)


--
The lifetime of any political organisation is about three years before
its been subverted by the people it tried to warn you about.

Anon.

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