Mike Bilow wrote in a message to LEE ARONER:
MB>      Second, it is the dumping ground for 
MB> transients on other IRQ lines which are shorter than the rated 
MB> recognition time, so IRQ 7 will frequently be signalled to 
MB> software if some card on another IRQ is defective.
 LA> Wow!  What an interesting tidbit. Explains a lot of odd little 
 LA> things over the years....Is this the default behaviour of the PIC?
 MB> Yes, and it has always been documented as such.
Thanks for the note - I just looked in my 1985 Intel databook for the 82C59A 
and here's the paragraph you describe:
"If no interrupt is present at step 4 of either sequence (i.e. the request 
was too short in duration) the 82C59A-2 will issue an interrupt level 7. Both 
the vectoring bytes and the CAS lines will look like an interrupt level 7 was 
requested." The sequence they're referring to is the handshaking between the 
PIC and the microprocessor... 
1. IRQ line goes high
2. PIC 'evaluates' the request and drives INT line to CPU
3. CPU sees the INT line, and pulses the INTA* line to the PIC
4. PIC chooses highest priority IRQ and does housekeeping until...
5. CPU pulses INTA* line again, during which the PIC writes a data byte
6. Cycle is done
Thanks again for pointing something out. Engineers (not necessarily Novell 
Engineers) like to know electronics trivia - sometimes it comes in useful! 
}
     Tom 
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