Hail!
Once you wrote to Glen McNabb:
 GM> CH>> Not quite. NMI is disableable on all 286+ motherboards by setting 
bit
 GM>> 7
 GM> CH>> of port 70h. On an XT, It's possible by reprogramming the 8255.
 GM>> It's possible
 GM> CH>> CLI has no effect on NMI, nor does disabling the PIC's.
 GM>> Of course not. Then, if you have a NMI at anytime it won't matter
 GM>> much. Failed parity is failed parity.
 CH> NMI is also used for math coprocessor exceptions in 286 and 386 designs,
   Not quite correct. 286 & 386 use IRQ13 for signalling FPU errors (though 
the default BIOS handler eventually calls INT 2 for compatibility). My BIOS' 
IRQ13 handler looks like this, for example:
        push    ax
        xor     al,al
        out     0F0h,al         ; clear FPU busy latch
        mov     al,20h
        out     0A0h,al         ; send EOI to the slave PIC
        jcxz    $+2
        jcxz    $+2
        out     20h,al          ; and to the master PIC
        pop     ax
        int     2
        iret
Farewell!
--- GoldED 2.50+
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