On (01 Mar 97) James Vahn wrote to Jerry Coffin...
 JC> reducing the requirements for cache coherency - i.e. when
 JC> one processor changes a location, the other processors might
 JC> not see that change immediately.  However, when we allow
 JC> this, we have to compensate for it in the programming
 JC> somehow, so it tends to be less popular.
 JV> So these individual processors run until a memory location is changed,
 JV> causing an interrupt and allowing the others to catch up, refreshing
 JV> their "view" of the memory pool and then continuing?
Yes and no - generally they use bus-snooping, so they only have to stop
and update when something gets changed that they have in their cache.
 JV> I'm not sure that I like that one.. The word "stumbling" comes to
 JV> mind.
Nobody _likes_ it - it's merely a necessary evil...
 JV> I wonder if that has anything to do with the somewhat incomprehensible
 JV> news in the local paper the other day- something about a 1gb/s
 JV> transfer mechanism. The article mentioned it might be used in ether-
 JV> networking but now from what you've said it sounds like it has an even
 JV> more intense use as a "chipset" of sorts (lacking a better term) within
 JV> the machine. Still somewhat clueless but a greater appreciation is mine,
 JV> thanks for the info.
This was probably related to networking - there are at least a couple of
companies out there working on gigabit Ethernet; among others, Andy
Bechtolshien, one of the chief designers of Sun's SPARC architecture,
now has another company working on it.
CPUs built for loosely coupled multiprocessor use generally include this
sort of thing on-chip.  For instance, the Inmos Transputer (may it rest
in peace) included more or less two processors on the chip: one did the
processing, the other was dedicated to the "networking" type stuff.  Of
course it also included an extremely high speed serial port for the
second processor to control.
    Later,
    Jerry.
... The Universe is a figment of its own imagination.
--- PPoint 1.90
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