Hi..
 SS> CH> Not quite. NMI is disableable on all 286+ motherboards by setting 
it
 SS> 7 of
 SS> CH> port 70h. On an XT, It's possible by reprogramming the 8255.
 SS> Wrong. IRQ masking port on XT was 0A0h, 8255 decoded ports 60h thru
 SS> 63h.
I'm afraid you are somewhat incorrect. Instead of starting a mud slinging 
contest, I will state my sources here. Please bear in mind that we are 
discussing the disabling of NMI's related to ram parity errors, not NMI in 
general.
1. Book: "The Undocumented PC" edition 1, page 671. Describes port 61h.
bit: R/W use
7     r  RAM Parity error present
6     r  I/O Parity error present
5     r  Output of timer 2
4     r  Refresh request clock / 2
3     rw enable I/O parity check - Generate NMI if error
2     rw enable ram parity check - Generate NMI if error
1     rw speaker data enabled
0     rw gate timer 2 on
This book makes copious references to NMI in chaper 17 'Interrupt control and 
NMI'. This book does not mention port A0h for NMI on an XT.
2. Ralf Brown's interrupt list, ports.lst, edition 56, table P102. 
(Essentially repeats data above).
Ralf Brown also documents port A0h. He says if you set bit 7 to a '1' then 
NMI is prevented from reaching the CPU.
The difference is that if you use port A0h to disable parity NMI's, you also 
disable NMI from the math coprocessor. If you use port 61h, you can disable 
parity-NMI's but still permit coprocessor NMI's through.
So it depends on what you want to achiveve. In the context of a discussion on 
ram parity NMI's, port 61h is clearly the better way to go about doing 
things, and that is why I wrote what I wrote, and why I feel your solution is 
somewhat worse. Granted, it doesn't make much difference if you don't have a 
mathco!
       Craig
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