Replying to a message of Sam Izzo to All:
 SI> on Creative's Web site that in their ISR, if the IRQ was
 SI> greater than 8, they signalled an EOI by outputting 20h to
 SI> PIC 2 and also did the usual 20h to PIC 1 Is this
 SI> necessary?  Here's some pseudocode of what they did:
Yes, it is necessary, because PIC2 actually signals to PIC1 that an interrupt 
has occurred, and it is actually PIC1 that informs the CPU that an interrupt 
has occurred. This is the heart of "INT02 redirection" that confuses many 
people. My memory is a bit vague, but I think this is how it works:
INT02 is not actually redirected anywhere; rather the INT09 bit on PIC2 is 
latched onto the INT02 line on the system bus, while the cascade bit on PIC2 
is latched onto the INT02 bit of PIC1. When PIC2 issues an interrupt, it 
raises the cascade bit, which in turn raises an INT02 on PIC1; it is actually 
PIC1 that raises the INT signal to the CPU by raising its cascade bit.
--- FleetStreet 1.21 NR
---------------