CH> Hi..
CH>  GM> CH> Not quite. NMI is disableable on all 286+ motherboards by
CH> setting bit
CH>  GM> 7
CH>  GM> CH> of port 70h. On an XT, It's possible by reprogramming the 8255.
CH>  GM> It's possible
CH>  GM> CH> CLI has no effect on NMI, nor does disabling the PIC's.
CH>  GM> Of course not. Then, if you have a NMI at anytime it won't matter
CH>  GM> much. Failed parity is failed parity.
CH> NMI is also used for math coprocessor exceptions in 286 and 386 designs,
CH> so an NMI handler needs to find out which source triggered it, and take
CH> the appropriate action, not just assume it must be a parity error.
In looking it up, (286/7 only) once and ESC code it recieved by the
processor, it either can activate one of several things. During the
time the 287 has control of the bus. The 286 is locked from the bus.
If an NMI or a RESET is asserted, it undoes the lock condition.
It's not that I'm so much that I disagree with you as it's quite
possible that the NMI could be held in a latch during processor
hold but 287 doesn't need it.
Glen.
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