Replying to a message of Scott McNay to Glen McNabb:
 GM>> segment) involves changing the SS and the SP. (usually) If
 GM>> the interupt occurs between loading those two registers
 SM> You sure of this?  Last I heard, as of the 80C86/80C88, that
 SM> had been fixed, so that interrupts would not occur until
 SM> after the instruction after a load of SS.  
I thought this bug was only present on the earliest of the 86/88 CPUs. 
 SM> and single-step through MOV SS,AX / MOV SP,BX (or something
 SM> similar), you'll find that the single-step jumps from the
 SM> MOV SS,?? to the instruction following MOV SP,??, unless
 SM> you explicitly force a breakpoint at the MOV SP,??.
That was definitely my experience with a V20; the 88 it replaced was an early 
one, and definitely did have the "feature". I cannot recall if my 286 ever 
did this, but I don't think so.
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