Hi Dennis,
You wrote to Coridon Henshaw:
DT>  LG> Nevertheless, based on what you've pointed out, which
DT>  LG> I cannot find fault
DT>  LG> with, I would then modify my earlier statements to
DT>  LG> recommend moving sound
DT>  LG> cards from IRQ10 to IRQ5, and leaving the NIC on IRQ10 -- would you
DT>  LG> agree?
DT>CH> Generally yes.
DT>CH>
DT>CH> However, since the interrupt controllers are programmable, I can't say 
f
DT>CH> sure that the default interrupt priorities are what OS/2 uses.
DT>CH>
DT>CH> Dennis Tonn?  Does OS/2 reprogram the PICs' priority settings?
DT> You can't really change the PIC's priorities, they are determined by
DT>the hardware wiring connected to the PIC(s). What you can do (and
DT>every OS I have seen does it) is change the "Interrupt number" that a
DT>line will generate when it hits the CPU. EG: Under Dos, the line
DT>connected to to IRQ 0 on the PIC comes in as Interrupt 8 in the CPU
DT>side handling.
You should look up the Intel 8259 PIC data (the one original PCs used,
now emulated in the support chipset). It is a very flexible device and
the start of the priority sequence can be programmed via software. The
default (reset) sequence is 0 to 7, and as the slave PIC in the AT
architecture is via IRQ 2 on the primary PIC, the reset priority is
initially 0,1,8,9(2),10,11,12,13,14,15,3,4,5,6,7.
However the PIC can be programmed to rotate the priority in one of two
ways, Specific Rotate and Auto Rotate. OS/2 uses the Specific Rotate
on the primary PIC and rotates the priority to make IRQ 3 the highest
priority, giving an interrupt priority sequence of
3,4,5,6,7,0,1,8,9(2),10,11,12,13,14,15 unless it finds the priority
already rotated by the BIOS.
A repeat from a posting I made in 1994:
The secondary PIC drives the irq 2 input on the first PIC. From the
Devcon CDROM or the DDK CDROM in PDDBASE.INF (OS/2 V2.1 Physical Device
Driver Reference), under Physical Parallel Port Device Driver/
subsection Parallel Port IRQ Performance:- "The Programmable Interrupt
Controller (PIC) has been rotated under OS/2 2.1, giving IRQ3 (serial
port) the highest priority in the system." So, the priority is
3,4,5,6,7,0,1,8,9(2),10,11,12,13,14 ,15. Somewhere else I seem to
remember reading that if OS/2 finds the priority already rotated by the
BIOS it leaves it alone (but I can't trace a reference for that).

All this is independant of where the interrupts are mapped in the
processor interrupt table.
DT> Don't confuse hardware IRQ wiring with generated Interrupt numbers.
I agree, that's a totally separate matter.
DT> Yes, OS/2 does change this Interrupt "numbering", it has to since
DT>protect mode operation "needs" the CPU Interrupt numbers (machine
DT>exceptions) used under real mode for hardware attachment (0 thru 1F).
DT> The PIC has been reprogrammed under OS/2 to reflect these lines as
DT>Interrupt 50 thru 57 (PIC0) and 70 thru 77 (PIC1).
The PIC does not control the mapping of physical interrupt to interrupt
table entry, the OS is totally responsible for that as the 80x86 family
(excluding the 8018x devices) has only _one_ hardware interrupt input
and associated handshake output in addition to the NMI. Equally, the
interrupt vector table has no effect on the priority of the interrupts,
it is no more than a vector table.
George
 * SLMR 2.1a * Wastebasket: Something to throw things near.
--- Maximus/2 3.01
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