From: Ed Beroset 
Subject: Re: extended memory
At 20:28 12/12/97, you wrote:
>
> DG>>  I ask, because I have been reading Intel specs for years,
> DG>> and haven't got a clue what this "Big Real" mode is
> DG>> supposed to be.
>
> SS>    It is still undocumented by Intel of course. :)
>
>I'm from Missouri. What is the opcode mnemonic to switch to this mode?
Serguei is correct.  In my experience it's more often called flat real
mode, since  it allows one access to the full 4G as a flat address space,
but it's the same thing.  There isn't any special opcode to switch into
this mode, since it's nothing more than a switch into, and then back out of
protected mode.  
> SS>    Plain RM but not BRM: first, the segment limits may be
> SS> set to 4G (or anything you like); second, you can change
> SS> B-bit in the segment descriptor caches so you segments can
> SS> be 32-bit even in RM (and AFAIK this can be done even with
> SS> CS though requires some tricks for correct interrupt
> SS> entering/ exitting)!
>
>No kidding, particularly since descriptors don't exist in "real" mode.
Not quite correct.  The descriptors aren't *accessible* from real mode, but
they still do exist and still have effect.  Also, Serguei isn't quite
correct when he says this is all undocumented by Intel.  Here's a
description about how to switch back from protected mode to real mode from
the Pentium Processor User's Manual, Volume 3:
-+--- extract begins
16.6.2. Switching Back to Real-Address Mode
The processor re-enters real-address mode if software clears the PE bit in
the CR0 register
with a MOV CR0 instruction. A procedure which re-enters real-address mode
should proceed
as follows:
1. If paging is enabled, perform the following sequence:
-- Transfer control to linear addresses which have an identity mapping
(i.e., linear
addresses equal physical addresses). Ensure the GDT and IDT are identity
mapped.
-- Clear the PG bit in the CR0 register.
-- Move zero into the CR3 register to flush the TLB.
2. Transfer control to a segment which has a limit of 64K (0FFFFH). This
loads the CS
register with the segment limit it needs to have in real mode. Ensure the
GDT and IDT
are in real-address memory (0-1Meg).
3. Load segment registers SS, DS, ES, FS, and GS with a selector for a
descriptor
containing the following values, which are appropriate for real mode:
-- Limit = 64K (0FFFFH)
-- Byte granular (G =0)
-- Expand up (E = 0)
-- Writable (W = 1)
-- Present (P =1)
-- Base = any value
Note that if the segment registers are not reloaded, execution continues
using the
descriptors loaded during protected mode.
4. Disable interrupts. A CLI instruction disables INTR interrupts. NMI
interrupts can be
disabled with external circuitry.
5. Clear the PE bit in the CR0 register.
6. Jump to the real mode program using a far JMP instruction. This flushes
the instruction
queue (of the Intel386 and Intel486 processors) and puts appropriate values
in the access
rights of the CS register. This step is not required on the Pentium
processor, however,
for downwards compatibility, a far JMP should be included as part of the
switching back
to real-address mode process.
7. Use the LIDT instruction to load the base and limit of the real-mode
interrupt vector
table.
8. Enable interrupts.
9. Load the segment registers as needed by the real-mode code.
-+--- extract ends
If you carefully read the note in step 3, you'll see that although there
isn't a neon sign saying "Flat Real Mode," it's certainly clear what will
happen if one were to leave some segment descriptors "large."  Also note
step 2, which refers to real mode GDT and IDT.  Clearly they still exist
and have meaning within real mode, even if they're not accessible. 
Check in the 1995 edition of the 80xxx snippets and you'll find a
subdirectory called "flat" which contains Herman Dullink's source code,
descriptions and examples of this mode.  
Ed
-!-
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