On 17/04/2018 06:24, Ahem A Rivet's Shot wrote:
>
>  Especially since the address and data busses are not exposed on pins
> where you can connect to them but buried deep inside the SOC.

With 4 processing units, and oodles of cache levels, not
to mention pipelined processing, that wouldn't be feasible
anyway. I had one of John Miller Kirkpatrick's (RIP) SCAMP
kits based upon the SC/MP processor which used clever tricks
to give a memory blinkenlights approach, but that was only
feasible with a single processing unit with a static processor
whereby the memory cycle could be extended indefinitely.
(Not possible with the Motorola chips which were dynamic)

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