Hi Auke,
You wrote to Bernhard Kuemel,
AR> BK> The intel 80x86 architecture has a different structure (which I
AR> BK> am not so familiar with). It uses only 1 interrupt line at the
AR> BK> processor and a 1 bit interrupt mask (which can be manipulated
AR> BK> with STI and CLI, AFAIK). Thus it also has only 1 priority level
AR> BK> for interrupts, IMHO. Several IRQ lines are mapped to this 1 IRQ
AR> BK> line and there is an interrupt byte which selects an adress from
AR> BK> the interrupt jump table which has 256 entries.
AR>This is only partially correct. The 80x86 architecture
AR>interfaces up to 15 interrupt lines via Priority Interrupt
AR>Controller (PIC) to the processor.
AR>Only the interrupt with the highest priority is passed on.
???? You're thinking of the special case of the IBM PC compatible :-(.
Bernhard is totally correct at the processor level for the 80x86 family.
Most of the processors in the family only have two interrupt lines, NMI
and INTR (the exceptions are the 8018x processors which in addition
to the NMI interrupt have an integrated PIC and can support 4 external
interrupts directly, or support 2 8259 PICs externally, each of which
can have up to 8 slave 8259 PICs to allow up to 128 external interrupt
sources). The processor architecture supports 256 interrupts via an
interrupt vector table, 0 to 31 (INT0 to INT1F) are reserved by Intel
for CPU instruction exceptions (and what problems IBM caused by not
honouring that reservation and using INT10 and up for software
interrupts for BIOS services :-(). The PIC used in the IBM PC, the 8259,
can support up to 64 interrupts by cascadeing a slave 8259 PIC from each
interrupt input pin of the master 8259 PIC.
The PC architecture is a limited case of the total support possible with
the 80x86 and 8259 PIC combination.
AR>There is some more nitty gritty but imho that all is way off topic ...
There is _much_ more nitty gritty, but as you say way off topic...
I just don't want other users of the echo to think that the 15 interrupt
case implemented by the IBM PC architecture represents the 80x86
interrupt architecture in general.
George
 * SLMR 2.1a * Wastebasket: Something to throw things near.
--- Maximus/2 3.01
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