On 09/03/2018 13:56, Tauno Voipio wrote:
> On 9.3.18 11:30, The Natural Philosopher wrote:

>> Even so, the method still reveals WHICH registers
>>
>> But it is not a feature of the ARM per se, merely a convention.
>>
>> I assume gcc follows it, but there is no gurantee
>
> GCC follows the ARM EABI specification:
>
>   - stack on 8 byte boundaries,
>   - arguments in r0 - r3
>   - return value in r0


Somewhat tidier than that for x64, which varies between Windows and
Linux. Windows has the simpler one, and passes the first four arguments
in rcx, rdx, r8 and r9.

So not only are the registers not consecutive, but they couldn't even
come up with a consistent naming scheme for the registers.

/And/ the stack has to be kept at 16-byte alignment, even though
individual parameters (the ones that have to go on the stack, and shadow
space for the first four), are all 8 bytes each. That is, it needs to be
16-byte aligned just before you execute 'call'.

Keeping track of that is a nightmare, and a real problem when writing
extensive ASM code that has to make calls to conforming functions.

Further (I don't know if this applies to ARM; does it have a separate
set of floating point registers?), floating point params need to be
passed in a corresponding floating point register instead, XMM0 to XMM3
(here, the names /are/ consistent, and they are consecutive!). For
variadic floating point arguments, they need to be passed in both.

Phew! And that's the easier Win64 ABI.

I guess simplicity of the call convention wasn't a priority.


--
bartc

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