On Sunday, 96/01/28, Mike Bilow wrote to David Noon about "Pl/i
Miscellanea" as follows:

MB> The motivation for having varying word sizes in the CPU was to
MB> allow  different units to be made with reasonable cost.  For 
MB> example, many machines of that era allowed 16-bit load and  store
MB> operations but only 8-bit arithmetic and logical  operations.

Hi Mike,

Chaining shorter word length operations does not require little-endian
architecture. The entry-level models of the IBM System/360 used 16-bit
ALU's to perform 32-bit arithmetic, all in big-endian format. Indeed,
the Intel uses big-endian inside the ALU. It is only little-endian in
RAM and external media.

Since the effective address and fetch length are calculated during
instruction decode, there is no addressing advantage to either scheme,
irrespective of word length.

Little-endian was just a perverse idea inside DEC that was "me-too-ed"
by Intel. [Indeed, DEC eschewed it for their better machines:
DECSystem-10 and DECSystem-20.] The price difference between early
Intel and Motorola microprocessors was a result of the overheads
incurred by a large, established corporation (Motorola) compared to a
lean, mean newcomer (Intel). [And perhaps some quality of manufacture
too.]

MB> The Intel floating point format follows the IEEE-754 
MB> standard, which handles reals as 64 bits.  As it happens, 
MB> the native Intel 80-bit real significantly exceeds the 
MB> precision required by IEEE-754.  If you need more precision 
MB> on reals than 80 bits, then you should have no expectation 
MB> that the hardware is going to support you.

But I was talking about extended precision, not double precision,
which is what IEEE-754 defines. The IBM mainframe supports -- in
hardware -- a mantissa of 109 to 112 bits (depending upon hexadecimal
normalisation) in a 16-byte quadruple word, which makes the Intel seem
rather puny. This degree of precision was introduced in the IBM 360/85
around 1969.

Regards

Dave


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