On (04 May 96) Rod Speed wrote to Keith Richardson...



KR> best of all, they pay big boys wages for me to do it

KR> too, if this is toilet cleaning, thats the life for me



 RS> Big boys dont get paid overtime. Only droids do.



big boys negotiate good deals for themselves. senile old farts sit back

in their comfortable chairs and whine about things beyond their

comprehension. i dont suppose that big boys got paid overtime in your

day rod, but this is now, and all sorts of funky things happen that

never used to when you were alive.



btw, i was browsing through ansi x3t10 2008d revision 6, which, of

course, you are aware is the standard that defines ata (ide), when the

following caught my eye. i have cut and pasted them straight from the

standard. i hope that this contributes to your understanding of the ata

(ide - eide) interface.



3.1.12 Master : In ATA-1, Device 0 has also been referred to as the

master. Throughout this document the term Device 0  is used.





3.1.17 Slave : In ATA-1, Device 1 has also been referred to as the

slave. Throughout this document the term Device 1  is used.



6 Interface register definitions and descriptions



6.1 Device addressing considerations



In traditional controller operation, only the selected device receives

commands from the host following selection.  In this standard, the

register contents go to both devices (and their embedded controllers).

The host discriminates between the two by using the DEV bit in the

Device/Head register.



Data is transferred in parallel either to or from host memory to the

device's buffer under the direction of commands previously transferred

from the host. The device performs all of the operations necessary to

properly write data to, or read data from, the media.  Data read from

the media is stored in the device's buffer pending transfer to the host

memory and data is transferred from the host memory to the device's

buffer to be written to the media.



The devices using this interface shall be programmed by the host

computer to perform commands and return status to the host at command

completion.  When two devices are daisy chained on the interface,

commands are written in parallel to both devices, and for all except

the EXECUTE DEVICE DIAGNOSTICS command, only the selected device

executes the command.  On an EXECUTE DEVICE DIAGNOSTICS command

addressed to Device 0, both devices shall execute the command, and

Device 1 shall post its status to Device 0 via PDIAG-.



Devices are selected by the DEV bit in the Device/Head register (see

6.2.8). When the DEV bit is equal to zero, Device 0 is selected.  When

the DEV bit is equal to one, Device 1 is selected.  When devices are

daisy chained, one shall be set as Device 0 and the other as Device 1.



that seems to be a bit at odds with this:-



 RS> Well, even the first ribbon cable with EIDE normally just has

 RS> a pretty crude buffer of the bus signals, the 'controller' is

 RS> on the drive itself, on the master drive in a pair.



corse people like seagate may consult you rather than the ansi docs

when designing new drives, but it does seem odd that they are on the

committee that wrote the spec, and your name never appears on the ide

developers' reflector. corse it could just mean that you had a massive

brain fart and are too anal to admit it, or it could just be that you

have as much idea of how these things work as the average sandfly.



                        Keith





... QWKs? We don' need no steenkin' QWKs.



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