Hi Pascal.

09-Oct-03 11:20:50, Pascal Schmidt wrote to Jasen Betts


 PS> Hi Jasen! :-)

 JB>> Having the pixels 4-byte alligned helps the CPU to address them
 JB>> and write them in a single operation. and results in a
 JB>> performance increase for pixel-orientated operations.

 PS> Actually, that doesn't work since the CPU memory bandwidth exceeds
 PS> the speed at which graphics memory can be accessed over the bus
 PS> (even AGP) anyway, and x86 hardware doesn't pay much misalignment
 PS> penalty. Intel even reduced the penalty for misaligned access on
 PS> the P4 on the grounds that lots of programs use them

still it takes at best two write cycles to write a 24 bit pixel
(an 8 bit write and a 16 bit write)  if the 16 bit write straddles a data-bus
boundary it'll take 3 cycles, and these cycles happen at the video-bus
speed not at the CPU speed.

with a 32 bit pixel it takes a single write and you're guaranteed to always
fit inside the bus bouandary.

OTOH these days if you're pushing single pixels around using the CPU you're probably
doing whatever graphics task the slow way.

 PS> The GPUs on the graphics card themselves do profit from 4-aligned
 PS> pixels, though. Having pixels three bytes long would require extra
 PS> complicated silicion design because that size cannot be handled by
 PS> mere shifts and masking out of bits as is possible with sizes that
 PS> are powers of 2.

yeah I guess they could go for a 24 bit data bus on the video card,
or something like that...

-=> Bye <=-

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