TIP: Click on subject to list as thread! ANSI
echo: c_plusplus
to: MICHAEL TOTH
from: RAJESH DHAWAN
date: 1997-08-17 14:11:00
subject: modem & serial ports

Hi Michael:
Hope you are still with me :)
The UART 16550 register summary contd.
Reg 6: Modem Status
 Bit 0 (CTS) change in CTS
 Bit 1 (DSR) change in DSR 
 Bit 2 (RI) change in Ring indication
 Bit 3 (DCD) change in DCD
 Bit 4 (CTS) CTS state
 Bit 5 (DSR) DSR state
 Bit 6 (RI) RI state
 Bit 7 (DCD) DCD state
___------------------------------------------------
FIFO Control Register (Reg 2)
When Reg 2 is used for writing it works as a FIFO control reg.
 Bit 0 Enable FIFOs
 Bit 1 Rx FIFO reset
 Bit 2 Tx FIFO reset
 Bit 3 DMA Mode select
 -----------------------------------
 Bit 7,6  Rx trigger level
 -----------------------------------
 00  1
 01  4
 10  8
 11  14
 -----------------------------------
=================================================================
Will let you have more of the 16550 after you have digested this:)
Rajesh
 
...
 * ATP/Linux 1.50 * When you go to the market, use your eyes, not your ears.
--- Maximus/2 3.01
---------------
* Origin: Kalptaru Net India. http://www.kalptaru.com . (6:606/31)

SOURCE: echomail via exec-pc

Email questions or comments to sysop@ipingthereforeiam.com
All parts of this website painstakingly hand-crafted in the U.S.A.!
IPTIA BBS/MUD/Terminal/Game Server List, © 2025 IPTIA Consulting™.