Hi Michael:
  Michael Toth,
  In a message on 12 August, you wrote to me :
MT> well i what to know every thing you could tell me.(about 16550)
MT>.  like. what every 
MT> bit of he register are for  ex.. bit 1 is for the data to be sent..
MT> .  or anything that you think would be of any help...
MT> what i am trying to do is write a com program that i can do almost 
MT> anything with..
Firstly, you must get your hands on the book 'C Programmer's Guide To
Serial Communications' by JOE CAMPBELL (ISBN-81-203-0938-3) Its a 
must-read for writing a COMM prog.
The UART 16550 register summary:
Reg 0: Receiver Buffer Register
Reg 0:  Transmitter Buffer Register
  Thus if you write a byte to the Reg 0 it gets serial
transmitted and when you read from it you get the serial data byte 
received. (Multiplexed functionality)
Reg 1: Interrupt Enable Reg (IER)
 Enables the four types of interrupts supported by the UART.
 
 Bit 0 (RxRDY) Set this bit if you want an interrupt on every
  new byte received in Reg 0
 Bit 1   (TBE)  Set this bit and you will get an interrupt when
  the transmit reg (Reg 0) is empty (i.e ready to accept
  more data for transmission)
 Bit 2 Interrupt on receive error (parity error, framing error,
  etc)
 Bit 3   (RS-232 Input) An interrupt is generated when any of the
  RS-232 input pins changes states (DTR, RTS, CTS, etc)
 Bit 4-7 Always 0
Reg 2: Interrupt Identification Register (IIR)
 Bit 0 A zero here means that an interrupt is pending.
 Bit 2  Bit 1 Interrupt Description
 ---------------------------------------
 1 1 Serialization error
 1 0 Received Data
 0 1 Transmit Buffer Empty
 0 0 RS-232 Input changed states
 --------------------------------------------
 Bit 3 When FIFOs are disabled this bit is 0, otherwise this bit
  is set to indicate that the pending transmit or receive
  interrupt was generated by a timeout.
 Bit 6,7 When FIFOs are enabled these bits are always set.
 
Reg 3: Data Format (Line Control)
 
 Bit 1 Bit 0 No. of Data Bits
  -------------------------------------------
 0 0 5
 0 1 6
 1 0 7
 1 1 8
 -------------------------------------------
 Bit 2 No of stop bits 0 = 1 stop bit  1 = 2 stop bits
 Bit 5,4,3 Parity
 -----------------------
 000  None
 001  ODD
 011  EVEN
 101  MARK
 111  SPACE
 -------------------------
 Bit 6 (BREAK) When 1, this bit forces the transmitter to a 
  logical zero state until a zero is written to it.
 Bit 7 (DLAB - Divisor Latch Bit Access) When this bit is 1,
  reg 0 and reg 1 become LSB and MSB Baud Rate Divisor 
  Latch registers.
Reg 4: RS-232 O/P Control (Modem control)
 Bit 0 (DTR) a 1 here sets the DTR line
 Bit 1 (RTS) 
 Bit 2 (GP01) User-definable output
 Bit 3 (GP02) same
 Bit 4 (local loopback)
Reg 5: Serialization status (Line status)
 Bit 0 RxRDY Indicates a byte waiting to be read from reg 0
 Bit 1   (Rx Overrun) 
 Bit 2 Parity error
 Bit 3 Framing error
 Bit 4 Break detect
 Bit 5 Tx Buffer Empty
 Bit 6 Tx Empty (All bytes sent)
 Bit 7 FIFO Dirty
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 * ATP/Linux 1.50 *   Les gens heureux me font chier -- Reiser 
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