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From: "Steven Levine" 
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@Date: Fri, 05 Dec 2003 08:25:25 -0800
Subject: Re: Contacting Ray Guinn
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In , on 12/05/03 
   at 10:00 AM, "visionsyswk"
 said:

>> Here's some the code I use to program the baud rate on some systems:
>> 
>>   /* Baud rate divisor = 1,843,200 / (Baud Rate * 16) */
>>   #define ACE_B2D(Rate)	((unsigned short)(1843200L/((long)
>Rate<<4)))

>This assumes a 16450 compatible device, configured very similar to 
>COM1/COM2; i.e. the maximum speed is 115,200 (1,843,200 / 16).

Yes.  This is old, ISA only code.  I posted it only as an example of how
initialization code could easily be incapabable of handling current UART
implementations.  I didn't even bother to mention that the code code is
totally unaware the the PCI bus exists.

>The multiplier is not reprogrammable on many cards anyway.

True, but it almost has to be to get beyond 115KB.  I pulled a datasheet
for an EXAR high-speed quad UART, at random, to see how they implemented
the extended data rates.  They provide a 1x/4x prescaler for input clock.

>> so it's probably limited to 450K baud,

>Why that special speed? I do not understand how to get to this value.

Because I had a senior moment and divided by the shift count.  Don't ask
my why. :-(

>No, Randy is not misinterpreting.

Then I misunderstood his explanation.

>In fact, Ray Gwinn had two typical boards from us while he developed 
>SIO2k version 2.01. When we made our simple tests with WARP 3, we had  a
>successfull transmission with 230,400 baud.

This I had no way of knowing.

>You do not need to reprogram any hardware multiplier. The approach is 
>much easier when you take a different look. Pseudo code:
>When loading the driver:
> enter internal loopback mode
> configure divisor to 1, 8N1
> transmit and count characters for one timer tick (~55 ms)
>  typical results are:
>    COM1 (factor 1, 115200): ca. 630
>    COM3 (factor 2, 230400): ca. 1250
>         (       4, 460800):     2500
>         (       8, 921600):     5000
>  It is easy to guess the correct factor N.
>  Save N.

Do you know if this is the algorithm Ray implemented?  I have no way of
knowing what he implemented, but this kind of counting is not so easy in
the OS/2 driver model.  Also, recent kernels have the ability to scale the
interrupt rate (I.e. CLOCKSCALE) so one can not depend on the 18.2Hz rate. 
That said, there are timer services available to the driver that would
allow this loop to be implemented.

>In the moment we have two different chipsets.
>Randy has our H-series, with 16C950 UARTs (http://www.oxsemi.com). We
>also have a different L-series, based on standard 16C550 UART.

Thanks.  I took a look at it to compare it with the EXAR.  It appears that
there's no real standard for extended BRG setup.  The embedded stuff I
currently maintain is still ISA based and we use 8 channel GTEK's to
offload the serial processing, but ISA slots are hard to come by and the
time may come were I need to implement PCI support as the old hardware
dies off.

>Anyway, if you are interested in data sheets or a sample board, feel free
>to contact me direct. I'll provide you with hardware to work on.

Thanks for the offer.  At the moment, I don't have time available to take
on another programming task.  However, I do have the source code for IBM's
COM.SYS.  I'll take a look at the implementation as time permits.

FWIW, the code and build tools are all available from the DDK site for the
cost of the free registration, so anyone is free to try to build a
modified version.  I have to suspect the required modifications are minor.

Regards,

Steven

-- 
----------------------------------------------------------------------
"Steven Levine"   MR2/ICE 2.41
#10183 Warp4/FP15/14.093c_W4
www.scoug.com irc.webbnet.info irc.fyrelizard.org #scoug (Wed 7pm PST)
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