Hi Coridon,
You wrote to Lawrence Garvin:
CH>On Tuesday April 21 1998 at 18:57, Lawrence Garvin wrote to Roy J. 
Tellason:
CH> LG> There is a minute amount of logicality to this default
CH> LG> configuration. When
CH> LG> responding to IRQs, the CPU gives priority to the lower numbered IRQ.
CH>That's not entirely true.
CH>Due to the cascaded nature of the IRQ chips, IRQs 9-15 generally have a 
high
CH>priority to IRQs 1-8. The exact priority is BIOS/OS selectable, and may 
chan
CH>from system to system.
Not quite correct for the default set up with the controllers in their
default state. IRQs 8 to 15 have a priority between IRQ 1 & IRQ 3 to
give a normal IRQ priority sequence of:
0,1,8,9(2),10,11,12,13,14,15,3,4,5,6,7
However, under OS/2 the normal interrupt priority is:
3,4,5,6,7,0,1,8,9(2),10,11,12,13,14,15
From my archive, back in March 1994 I wrote to David Wright:
PIC drives the irq 2 input on the first PIC. From the Devcon
CDROM or the DDK CDROM in PDDBASE.INF (OS/2 V2.1 Physical Device
Driver Reference), under Physical Parallel Port Device Driver/
subsection Parallel Port IRQ Performance:- "The Programmable
Interrupt Controller (PIC) has been rotated under OS/2 2.1,
giving IRQ3 (serial port) the highest priority in the
system." So, the priority is 3,4,5,6,7,0,1,8,9(2),10,11,12,13,14
,15. Somewhere else I seem to remember reading that if OS/2
finds the priority already rotated by the BIOS it leaves it alone
(but I can't trace a reference for that).
George
 * SLMR 2.1a * Wastebasket: Something to throw things near.
--- Maximus/2 3.01
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