RM> FIFO. When the FIFO becomes full, IRQ7 is asserted and a routine 
 RM> written in assembler reads all the time slices from the FIFO which is 
 RM> adressed at D000:0000.  The FIFO usually contains 400 16-bit words 
 
    Is it possible to  1) set up the board to trigger an interrupt before
the FIFO is full, and 2) determine how full the FIFO is when the interrupt
does get serviced, and read only that much? If so, this could relax
interrupt latency requirements greatly, at the expense of having to service
more interrupts, but since the interrupts are only happening about 1/sec,
that's not a pressing problem. I think the ceiling on interrupt latency for
OS/2 is on the order of 4msec, which is a bit longer than the 3.3msec
between counts.
 
    BTW, could the board not be set up to sample at a lower rate? As I
understand the situation, it sounds like you're just taking the total count
for each 1.33sec period - e.g. intermediate values aren't of any importance
on their own. Or is the count rate high enough that the 16-bit counts may
overflow if the sampling period were to be much longer?

--- Maximus/2 2.01