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| subject: | Real-time Acquisition |
In a message on 01-16-95, Luns Tee said to Robert Mcisaac: LT> I think the ceiling on interrupt latency for OS/2 is on the order of LT> 4msec, which is a bit longer than the 3.3msec between counts. Actually, that's almost the documented ceiling on the _thread dispatch delay_, not the interrupt latency. For interrupts the number is something like 400 microseconds "guaranteed" with typical values more like 70 microseconds, all depending on the processor of course. ___ * MR/2 * Now cruising at Warp 3! --- QScan v1.14b / 01-0348* Origin: FidoNet: CRS Online, Toronto, Ontario (1:229/15) SEEN-BY: 12/2442 620/243 624/50 632/348 640/820 690/660 711/409 410 413 430 SEEN-BY: 711/807 808 809 934 942 949 712/353 515 713/888 800/1 7877/2809 @PATH: 229/15 3615/50 229/2 12/2442 711/409 808 809 934 |
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