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| subject: | Real-time Acquisition |
Hello Peter! Replying to a message of Peter Hansen to Luns Tee: PH> In a message on 01-16-95, Luns Tee said to Robert Mcisaac: LT>> I think the ceiling on interrupt latency for OS/2 is on the order of LT>> 4msec, which is a bit longer than the 3.3msec between counts. PH> Actually, that's almost the documented ceiling on the _thread dispatch PH> delay_, not the interrupt latency. For interrupts the number is PH> something like 400 microseconds "guaranteed" with typical values more PH> like 70 microseconds, all depending on the processor of course. ___ Where are you getting this information? I would be defintely interested in reading whatever material will give me this sort of information. --- FleetStreet 1.00 NR* Origin: The Land Of Mordor/2 - (904) 532-0471 (1:3618/7) SEEN-BY: 12/2442 620/243 624/50 632/348 640/820 690/660 711/409 410 413 430 SEEN-BY: 711/807 808 809 934 942 949 712/353 515 713/888 800/1 7877/2809 @PATH: 3618/7 5 12 3615/50 229/2 12/2442 711/409 808 809 934 |
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