Quoting Peter Watney to Robert Bilton

--SNIP--
PW>Fortunately for me I have always been able to use other people's comms
PW>drivers, so I have never actually had to program the beastly things. 
PW>The cascaded 8259s that control the precedence and manner in which the
PW>programmable interrupts are handled are programmed using system ports:
PW>020 - 03F for Interrupt Controller No 1; and 0A0 - 0Bf for Interrupt
PW>controller No 2 
PW>I think I am right in saying that ports 020 and 0A0 are the 'command
PW>ports' for the chips, and that ports 021 & 0A1 are the ports to which
PW>the Mask Interrupt bits are sent that enable/disable the various IRQs,
PW>which are something like:
PW>in the Interrupt Controller No 1:
PW>IRQ 4 (COM1:);
PW>IRQ 3 (COM2:);
PW>IRQ 2 (to Interrupt Controller No 2);
PW>In the Interrupt Controller No 2:
PW>IRQ 4 (COM3:);
PW>IRQ 3 (COM4:).
Not quite. The second 8259 handles IRQs 8-15, which are not used for com
ports by default. The first controls IRQs 0-7, including the three you
mention above.

Fitz

... Spaghetti code = job security.
                                                                                 
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