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from: `Derek W. Keoughan`
date: 2006-01-15 09:03:34
subject: Re: [OS2HW] SMP Options.

On Tue, 14 Feb 2006 22:36:18 +0000 (GMT), Alastair Budge-Reid wrote:

>One for the hardware buffs.  
>
>Running ACP2 on server I have the option of using quad Xeon PIIs with
1Mb L2 cache 
>or quad Xeon PIIIs with 512Kb L2 cache.  I have no benchmarking software but, 
>assuming same speed, can anybody please advise which setup will give better 
>performance.   Is one clearly way ahead of the other?
>
>Would using the machine for multimedia application make any difference?

You're going waaaaay back in time, but I'd venture that raw clock speed
will win out over cache size - you don't mention the clock speeds, so I
can't make much in the way of an "authoritative" statement...

P2 was 233 to 400MHz, if memory serves, and P3 ramped up to just over
1GHz - it really depends on what you have there, of course - with a
miniscule difference in clock rates, the cache will be more of a factor
- and what you're actually doing with the system will be even more of a
factor.

The software, of course, would have to be multi-threaded so the OS can
split the load among the four CPUs.

Either way - it might not be worth the hydro to run it - a single-CPU
of current generation will likely run circles around it, and use less
juice.  It's that kind of economy that's kept me from putting some
older AthlonMP CPU's to use on the distributed.net project...

-Derek



Derek W. Keoughan,
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